Concerning the problem that the development cycle of existing elliptic curve algorithm system level design is long and the performance-overhead indicators are not clear, a method of Hardware/Software (HW/SW) co-design based on Electronic System Level (ESL) was proposed. This method presented several HW/SW partitions by analyzing the theories and implementations of SM2 algorithm, and generated cycle-accurate models for HW modules with SystemC. Module and system verification were proposed to compare the executing cycle counts of HW/SW modules to obtain the best partition. Finally, the ESL models were converted to Rigister Transfer Level (RTL) models according to the CFG (Control Flow Graph) and DFG (Data Flow Graph) to perform logic synthesis and comparison. In the condition of 50 MHz,180 nm CMOS technology, when getting best performance,the execute time of point-multiply was 20 ms, with 83 000 gates and the power consuption was 2.23 mW. The experimental result shows that the system analysis is conducive to performance and resources evaluation, and has high applicability in encryption chip based on elliptic curve algorithm. The embedded SoC (System on Chip) based on this algorithm can choose appropriate architecture based on performance and resource constraints.